D Latch
The D latch is a level-sensitive storage element, the transparent cousin of the D flip-flop. While the Enable input is high the latch is 'transparent' and Q simply follows D; when Enable goes low the latch 'closes' and holds the last value D had. Asynchronous PRE and CLR force Q immediately (CLR wins). Because it responds to the whole high level of Enable rather than to a single edge, a latch is faster and smaller than an edge-triggered flip-flop but far more sensitive to input glitches, so it is used deliberately, for example in two-phase clocking and register files.
Transparent versus opaque
Connect D to a switch, Enable to another, and Q to an LED. With Enable high, moving the switch changes Q instantly, the latch is transparent. Set Enable low and the LED freezes at whatever D was, ignoring further switch changes. The characteristic table below captures both phases.
| EN | D | Q |
|---|---|---|
| 0 | X | Q (hold) |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Latch versus flip-flop timing
Watch the waveform: while Enable is high, Q tracks every wiggle of D, so a glitch on D during that window passes straight through. An edge-triggered flip-flop, by contrast, would sample D only at one instant and reject the glitch. This is the key reason synchronous designs prefer flip-flops and use latches only where transparency is wanted on purpose.
A word-wide latch register
Put several D latches side by side and tie their Enable lines together. A single pulse on the shared Enable captures a whole multi-bit word at once, exactly how an address or data bus is held stable while the rest of a system reads it. Latch-based registers like this cost less area than flip-flop registers, which is why they appear in dense structures such as register files and caches.
Citations
- Wakerly, J. F. (2018). Digital design: Principles and practices (5th ed.). Pearson.. Reference 1
- Shannon, C. E. (1938). A symbolic analysis of relay and switching circuits. Transactions of the American Institute of Electrical Engineers, 57(12), 713-723.. Reference 2
- Mano, M. M., & Ciletti, M. D. (2018). Digital design: With an introduction to the Verilog HDL, VHDL, and SystemVerilog (6th ed.). Pearson.. Reference 3