Bus Splitter
A bus is a bundle of wires that carry a multi-bit value as one line. The Splitter decomposes an incoming N-bit bus into N individual 1-bit lines, so bit i of the bus becomes output i. It performs no logic and adds no delay: it is purely a wiring convenience that lets you route or observe each bit separately. Because the simulator already supports fanout, the same signal source can feed the bus and every split bit stays in sync with it.
Splitting a 4-bit bus
Set the Splitter's bit width to 4 and wire a 4-bit bus into its single input. The four outputs then carry b0, b1, b2 and b3 (least significant bit first). Output i simply exposes bit i of the bus value, so a bus value of 1011 produces b0=1, b1=1, b2=0, b3=1.
| Bus | b3 | b2 | b1 | b0 |
|---|---|---|---|---|
| 0000 | 0 | 0 | 0 | 0 |
| 1011 | 1 | 0 | 1 | 1 |
| 1111 | 1 | 1 | 1 | 1 |
Bit indexing, LSB first
The Splitter follows the least-significant-bit-first convention: output index 0 is the LSB and index N-1 is the MSB. This matches how the bus value is interpreted as a binary number, so tapping output 0 always gives you the units bit. Keeping a consistent bit order is essential when you feed the split lines into an adder, comparator or address decoder.
Turning a bus into per-bit indicators
Drive the Splitter from a 4-bit Counter's bus output and connect each split line to its own LED. As the counter advances, the LEDs display the running value in binary, giving you a live per-bit readout without any extra logic. This is the standard pattern for observing an internal bus, driving a bank of single-bit sinks, or breaking a word apart before selective processing; to go the other way and merge single bits back into a bus, wire them onto a common bus line instead.
Citations
- Harris, D. M., & Harris, S. L. (2012). Digital design and computer architecture (2nd ed.). Morgan Kaufmann. Reference 1
- Mano, M. M., & Ciletti, M. D. (2018). Digital design: With an introduction to the Verilog HDL, VHDL, and SystemVerilog (6th ed.). Pearson. Reference 2