Bus Merger
A bus is a bundle of wires that carry a multi-bit value as one line. The Merger composes N individual 1-bit lines into one outgoing N-bit bus, so input i becomes bit i of the bus. It performs no logic and adds no delay: it is purely a wiring convenience that lets you combine separately-driven signals into a single bus line. It is the Splitter's exact counterpart — where the Splitter breaks a bus apart, the Merger puts one back together.
Merging four 1-bit lines
Set the Merger's bit width to 4 and wire four separate 1-bit lines into its four inputs — in0, in1, in2 and in3 (least significant bit first). The single output then carries the composed bus, where input i simply becomes bit i of the bus value, so in0=1, in1=1, in2=0, in3=1 produces the bus value 1011.
| in3 | in2 | in1 | in0 | Bus |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0000 |
| 1 | 0 | 1 | 1 | 1011 |
| 1 | 1 | 1 | 1 | 1111 |
Bit indexing, LSB first
The Merger follows the least-significant-bit-first convention: input index 0 becomes the LSB of the bus and index N-1 becomes the MSB. This matches how the Splitter numbers its outputs, so a bus split apart and merged back together with matching indices round-trips to the same value. Keeping the same bit order at both ends is essential whenever you split a bus, process the individual bits, and merge them back.
Turning per-bit sources into a bus
Drive four Switches into a Merger and feed its 4-bit output into a 7-Segment Display's decoder input. Toggling the switches now composes a value bit by bit and shows it as a single digit, the standard pattern for building a bus out of independently-controlled sources such as switches, sensors, or the outputs of several small subcircuits. To go the other way and break a bus back into individual bits, use the Splitter instead.
Citations
- Harris, D. M., & Harris, S. L. (2012). Digital design and computer architecture (2nd ed.). Morgan Kaufmann. Reference 1
- Mano, M. M., & Ciletti, M. D. (2018). Digital design: With an introduction to the Verilog HDL, VHDL, and SystemVerilog (6th ed.). Pearson. Reference 2