Tri-state buffer
A switchable connection rather than a logic function: while EN is HIGH the output Q repeats the input D unchanged, and while EN is LOW the output stops driving altogether and floats at high impedance (Z). That third state is what lets several devices share one bus — each drives it only when enabled, and the rest stay out of the way.
The three states
Wire a switch to D and another to EN, and an LED to Q. With EN HIGH the LED follows D exactly, as if the buffer were a plain wire. Drop EN to LOW and Q stops driving: it is no longer 0 or 1, it is disconnected. Note that Z is not the same as 0 — nothing is holding the line down, it is simply left floating.
| EN | D | Q |
|---|---|---|
| 0 | 0 | Z |
| 0 | 1 | Z |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Two sources, one bus
Put two tri-state buffers side by side and join their outputs to the same wire. Drive the two EN inputs from a signal and its inverse, so exactly one buffer is enabled at any moment. The shared wire then carries whichever source is currently selected. This is the whole idea behind a data bus, and it only works because the disabled buffer truly lets go of the line instead of driving a 0 against the other source.
Buses and contention
Raise the buffer's bit width and it gates a whole bus at once, every line switching together. The failure mode to watch for is contention: if two buffers are enabled at the same time and disagree, they fight over the same wire. Real hardware can be damaged by that; here the conflict is flagged instead. The usual guard is a decoder driving the enables, which by construction asserts only one of them.
Citations
- Mano, M. M., & Ciletti, M. D. (2018). Digital design: With an introduction to the Verilog HDL, VHDL, and SystemVerilog (6th ed.). Pearson. Reference 1
- Harris, D. M., & Harris, S. L. (2012). Digital design and computer architecture (2nd ed.). Morgan Kaufmann. Reference 2