Priority encoder
A priority encoder outputs the binary index of the highest-priority input that is active, ignoring any lower-priority inputs that are also active. A valid flag distinguishes the all-zero case from a genuine index of 0. It is the inverse of a decoder and the standard way to arbitrate competing requests.
4-to-2 priority encoder
Four request lines produce a 2-bit code plus a valid bit V. When both I2 and I1 are active, the higher-priority I2 wins and the code is 10. If no input is active, V is 0.
| I3 | I2 | I1 | I0 | V | A1 | A0 |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | - | - |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| 0 | 0 | 1 | x | 1 | 0 | 1 |
| 0 | 1 | x | x | 1 | 1 | 0 |
| 1 | x | x | x | 1 | 1 | 1 |
8-to-3 priority encoder
Eight inputs collapse to a 3-bit code. With I5 and I2 active, the encoder reports 101 because I5 has the higher index. Adding an enable-in and enable-out lets several encoders cascade into a larger one.
Interrupt controller
When several devices raise interrupts at once, a priority encoder turns the request lines into the binary vector of the most urgent one, which the CPU uses to jump to the right handler. This is the heart of classic interrupt controllers such as the 8259.
Citations
- Shannon, C. E. (1938). A symbolic analysis of relay and switching circuits. Reference 1
- Texas Instruments (2003). SN74HC148: 8-line to 3-line priority encoders [Data sheet]. Reference 2
- Mano, M. M., & Ciletti, M. D. (2018). Digital design: With an introduction to the Verilog HDL, VHDL, and SystemVerilog (6th ed.). Pearson.