Parity checker
A parity checker recomputes the parity of a received word and compares it against the transmitted parity bit. A mismatch means an odd number of bits flipped, so it raises an error flag. Single-bit parity detects any odd-weight error but cannot locate or correct it.
Detecting an even-parity error
Under even parity the total number of ones in data plus parity must be even. Data 001 with P=0 has a single one, an odd total, so the checker flags an error. When the counts match, the error output stays low.
| Data | P | Error |
|---|---|---|
| 000 | 0 | 0 |
| 001 | 1 | 0 |
| 001 | 0 | 1 |
| 101 | 0 | 0 |
| 111 | 0 | 1 |
When parity matches
Data 101 has two ones; with even parity the expected check bit is 0, so P=0 gives an even total and no error. The checker only asserts its flag when the recomputed parity differs from the received bit.
Error detection on a link
At the receiving end of a UART, bus or memory read the checker re-derives parity and flags corrupted words so they can be retransmitted or discarded. It catches all single-bit and odd-weight errors; guaranteeing correction requires the multi-bit codes Hamming introduced.
Citations
- Hamming, R. W. (1950). Error detecting and error correcting codes. Reference 1
- Texas Instruments (2003). CD74HC280: 9-bit odd/even parity generator/checker [Data sheet]. Reference 2
- Wakerly, J. F. (2018). Digital design: Principles and practices (5th ed.). Pearson.